CMP slurries and pads: Overview
Why chips must be polished flat after every layer
What this tab covers What the chemical is, how big its market is, what it is used for (with shares, volumes, why it wins and what could replace it), and its chain from raw material to end user. Ends with three things to remember.Chemical mechanical planarisation (CMP) polishes a wafer flat after each deposition so the next layer can be patterned. A rotating polyurethane pad and a slurry of nanoscale abrasive (ceria, colloidal silica or alumina) in a chemical solution remove material at nanometre precision. Advanced chips need dozens of CMP steps, and hybrid bonding in advanced packaging adds more. The market was about $3.6 billion in 2025: $2.14 billion slurries and $1.46 billion pads. Fujifilm leads slurries and DuPont pads. India has no producer.
Volume not published as tonnage Market value about $3.6 billion (2025): slurries $2.14 billion, pads $1.46 billion; up 6% from 2024 Growth 8.6% a year through 2029 (combined); metal CMP consumables (cobalt, molybdenum, ruthenium) forecast up 94% over five years TECHCET CMP Consumables report summary via DRI (2025); TECHCET via Semiconductor Digest (May 2024)Key uses
| Use | Share | Annual volume | Why this commodity | Alternatives |
|---|---|---|---|---|
| Dielectric and shallow-trench isolation polishing (ceria and colloidal silica slurries) | n/a | not publishedbasis | Ceria reacts chemically with silicon dioxide and removes it fast and selectively against silicon nitride, which suits STI and interlayer dielectric steps. 3D NAND, with hundreds of oxide layers, uses a lot. TECHCET via DRI (2025); TECHCET via Semiconductor Digest (2024) | Fixed-abrasive pads Etch-back processes (less planar) |
| Copper and barrier polishing (interconnects) | n/a | not publishedbasis | Copper wiring is made by damascene: trenches are overfilled with copper and the excess is polished off, followed by a barrier step. Every metal level in a logic chip needs this. TECHCET via Semiconductor Digest (May 2024) | None at scale for damascene copper |
| Tungsten and new metals (cobalt, molybdenum, ruthenium) | n/a | not publishedbasis | Tungsten plugs and new contact metals at advanced nodes each need their own slurry chemistry with oxidisers such as hydrogen peroxide. TECHCET via Semiconductor Digest (May 2024) | Selective deposition reducing CMP steps (indicative) |
| Polishing pads (polyurethane) | 40.6% | not publishedbasis | Porous polyurethane pads carry slurry and set the mechanical part of polishing. Pad texture and hardness are matched to each step, and pads wear out after hundreds to thousands of wafers (indicative). TECHCET via DRI (2025) | Fixed-abrasive pads |
| Advanced packaging (TSV, hybrid bonding, redistribution layers) | n/a | not publishedbasis | Hybrid bonding of chip stacks for AI memory and chiplets needs extremely flat copper and oxide surfaces, extending CMP from front-end fabs into packaging. TECHCET via DRI (2025) | Conventional bump bonding (no CMP) |
From raw material to user
- Abrasive particles Ceria from rare-earth separation, colloidal silica from sodium silicate or silicon alkoxides, fumed silica and alumina are made to tight nanoscale sizes (indicative).
- Slurry formulation Particles are dispersed in water with oxidisers (hydrogen peroxide), complexing agents, corrosion inhibitors and pH buffers, and filtered to remove large particles that scratch wafers.
- Pad manufacture Polyurethane is cast or moulded with pores and grooves; DuPont supplies over half the world's pads (TECHCET 2024).
- Polishing CMP tools from Applied Materials and Ebara press wafers onto rotating pads while slurry flows; endpoint detection stops polishing on target.
- Post-CMP clean Brushes and chemistries remove slurry residue; wafers then go to the next deposition.
- Waste Spent slurry becomes wastewater with suspended nanoparticles that fabs must treat (indicative).
Made from (commodity table)
REE Rare earthsThree things to know
- CMP consumables were about $3.6 billion in 2025: slurries $2.14 billion and pads $1.46 billion (TECHCET).
- Two firms dominate: Fujifilm held 31% of slurries and DuPont over 50% of pads (TECHCET via Semiconductor Digest, 2024).
- Ceria slurry links chips to rare earths, and TECHCET flagged the need to qualify alumina, ceria and silica sources outside China and Russia (2024).